RegViz: Visualize GTUPSR Bitfield

Renesas Electronics /R7FA2E1A9 /GPT320 /GTUPSR

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Interpret as GTUPSR

USGTRGAR=0, USCBFAH=0, USCAFBH=0, USELCC=0, USCBRAL=0, USGTRGBR=0, USCAFBL=0, USELCB=0, USCARBH=0, USGTRGBF=0, USGTRGAF=0, USCARBL=0, USELCD=0, USELCA=0, USCBFAL=0, USCBRAH=0

Description

General PWM Timer Up Count Source Select Register

Fields

USGTRGAR	GTETRGA Pin Rising Input Source Counter Count Up Enable 0 (0): Counter count up disabled on the rising edge of GTETRGA input 1 (1): Counter count up enabled on the rising edge of GTETRGA input
USGTRGAF	GTETRGA Pin Falling Input Source Counter Count Up Enable 0 (0): Counter count up disabled on the falling edge of GTETRGA input 1 (1): Counter count up enabled on the falling edge of GTETRGA input
USGTRGBR	GTETRGB Pin Rising Input Source Counter Count Up Enable 0 (0): Counter count up disabled on the rising edge of GTETRGB input 1 (1): Counter count up enabled on the rising edge of GTETRGB input
USGTRGBF	GTETRGB Pin Falling Input Source Counter Count Up Enable 0 (0): Counter count up disabled on the falling edge of GTETRGB input 1 (1): Counter count up enabled on the falling edge of GTETRGB input
USCARBL	GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable 0 (0): Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0
USCARBH	GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable 0 (0): Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1
USCAFBL	GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable 0 (0): Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0 1 (1): Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0
USCAFBH	GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 0 (0): Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 1 (1): Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1
USCBRAL	GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable 0 (0): Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0
USCBRAH	GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable 0 (0): Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1
USCBFAL	GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable 0 (0): Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0 1 (1): Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0
USCBFAH	GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable 0 (0): Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1 1 (1): Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1
USELCA	ELC_GPTA Event Source Counter Count Up Enable 0 (0): Counter count up disabled at the ELC_GPTA input 1 (1): Counter count up enabled at the ELC_GPTA input
USELCB	ELC_GPTB Event Source Counter Count Up Enable 0 (0): Counter count up disabled at the ELC_GPTB input 1 (1): Counter count up enabled at the ELC_GPTB input
USELCC	ELC_GPTC Event Source Counter Count Up Enable 0 (0): Counter count up disabled at the ELC_GPTC input 1 (1): Counter count up enabled at the ELC_GPTC input
USELCD	ELC_GPTD Event Source Counter Count Up Enable 0 (0): Counter count up disabled at the ELC_GPTD input 1 (1): Counter count up enabled at the ELC_GPTD input

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